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Serial (RS232) Port Pins and Registers
This is an overview of all serial port (RS232) registers, including the pin-out of
a SUB-D 25 and SUB-D 9 connection.
SERIAL PORT PINS
| SUB-D 25 pin# | SUB-D 9 pin# | | |
| 2 | 3 | TX | Transmit Data |
| 3 | 2 | RX | Receive Data |
| 4 | 7 | RTS | Request To Send |
| 5 | 8 | CTS | Clear To Send |
| 6 | 6 | DSR | Data Set Ready |
| 7 | 5 | GND | Signal Ground |
| 8 | 1 | CD | Carrier Detect |
| 20 | 4 | DTR | Data Terminal Ready |
| 22 | 9 | RI | Ring Indicator |
SERIAL PORT ADDRESSES
| PORT | common address | IRQ |
| COM 1 | 3F8h | 4 |
| COM 2 | 2F8h | 3 |
SERIAL PORT REGISTER OVERVIEW
| BASE ADDRESS | DLAB | RD/WR | Abr. | NAME |
| + 0 | 0 | WR | - | Transmitter Holding Buffer |
| 0 | RD | - | Receiver Buffer |
| 1 | RD/WR | - | Divisor Latch Low Byte |
| + 1 | 0 | RD/WR | IER | Interrupt Enable Register |
| 1 | RD/WR | - | Divisor Latch High Byte |
| + 2 | - | RD | IIR | Interrupt Identification Register |
| - | WR | FCR | FIFO Control Register |
| + 3 | - | RD/WR | LCR | Line Control Register |
| + 4 | - | RD/WR | MCR | Modem Control Register |
| + 5 | - | RD | LSR | Line Status Register |
| + 6 | - | RD | MSR | Modem Status Register |
| + 7 | - | RD/WR | - | Scratch Register (general purpose) |
DLAB - Divisor Latch Access Bit:
This is a bit which must be use to either set the BAUD speed (f0 = 1.8432 MHz / 16 (prescaler) = 115200; e.g.
115200 / 9600 = 12 => latch high byte: 00h; low byte: 0Ch) or to access the Interrupt Enable Register.
DLAB is found in the Line Control Register (LCR).
ADDRESS: BASE + 1 - RD/WR - DLAB=0 - NAME: Interrupt Enable Register (IER)
| bit # | name |
| 0 | Enable Received Data Available Interrupt |
| 1 | Enable Transmitter Holding Register Empty Interrupt |
| 2 | Enable Receiver Line Status Interrupt (INT in LSR - Line Status Register) |
| 3 | Enable Modem Status Interrupt (INT in MSR - Modem Status Register) |
| 4 | Enables Sleep Mode (16750) |
| 5 | Enables Low Power Mode (16750) |
| 6 | Reserved |
| 7 | Reserved |
ADDRESS: BASE + 2 - READ ONLY - NAME: Interrupt Identification Register (IIR)
| bit # | |
| 0 | 0 | | Interrupt Pending |
| 1 | | No Interrupt Pending |
| 1 & 2 | B2 | B1 | INT type (priority) |
| 0 | 0 | Modem Status Interrupt (4) |
| 0 | 1 | Transmitter Holding Register Empty Interrupt (3) |
| 1 | 0 | Received Data Available Interrupt (2) |
| 1 | 1 | Receiver Line Status Interrupt (1) |
| 3 | 0 | | Reserved on 8250, 16450 |
| 1 | | 16550 Time-out Interrupt Pending |
| 4 | | | Reserved |
| 5 | | | 64 Byte Fifo Enabled (16750 only) |
| 6 & 7 | B6 | B7 | |
| 0 | 0 | No FIFO |
| 0 | 1 | FIFO Enabled but Unusable |
| 1 | 1 | FIFO Enabled |
ADDRESS: BASE + 2 - WRITE ONLY - NAME: FIFO Control Register (FCR)
| bit # | |
| 0 | | | Enable FIFOs |
| 1 | | | Clear Receive FIFO |
| 2 | | | Clear Transmit FIFO |
| 3 | | | DMA Mode Select. Change status
of RXRDY &
TXRDY pins from mode 1 to mode 2. |
| 4 | | | Reserved |
| 5 | | | Enable 64 Byte FIFO (16750 only) |
| 6 & 7 | B7 | B6 | Interrupt Trigger Level |
| 0 | 0 | INT on 1 byte received |
| 0 | 1 | INT on 4 bytes received |
| 1 | 0 | INT on 8 bytes received |
| 1 | 1 | INT on 14 bytes received |
ADDRESS: BASE + 3 - RD/WR - NAME: Line Control Register (LCR)
| bit # | |
| 0 & 1 | B1 | B0 | | Word Length |
| 0 | 0 | | 5 Bits |
| 0 | 1 | | 6 Bits |
| 1 | 0 | | 7 Bits |
| 1 | 1 | | 8 Bits |
| 2 | 0 | | | One Stop Bit |
| 1 | | | 2 Stop bits for words of length
6,7 or 8 bits or
1.5 Stop Bits for Word lengths of 5 bits. |
| 3, 4
& 5 | B5 | B4 | B3 | |
| X | X | 0 | No Parity |
| 0 | 0 | 1 | Odd Parity |
| 0 | 1 | 1 | Even Parity |
| 1 | 0 | 1 | High Parity (parity bit constantly 1) |
| 1 | 1 | 1 | Low Parity (parity bit constantly 0) |
| 6 | | | | Set Break Enable |
| 7 | 1 | | | Divisor Latch Access |
| 0 | | | Access to Receiver buffer,
Transmitter buffer
& Interrupt Enable Register |
ADDRESS: BASE + 4 - RD/WR - NAME: Modem Control Register (MCR)
| bit # | name |
| 0 | Force Data Terminal Ready |
| 1 | Force Request to Send |
| 2 | Aux Output 1 |
| 3 | Aux Output 2 |
| 4 | LoopBack Mode |
| 5 | Autoflow Control Enabled (16750 only) |
| 6 | Reserved |
| 7 | Reserved |
ADDRESS: BASE + 5 - READ ONLY - NAME: Line Status Register (LSR)
| bit # | name |
| 0 | Data Ready |
| 1 | Overrun Error |
| 2 | Parity Error |
| 3 | Framing Error |
| 4 | Break Interrupt |
| 5 | Empty Transmitter Holding Register (TX register empty) |
| 6 | Empty Data Holding Registers (TX & shift register empty) |
| 7 | Error in Received FIFO (1 if break, parity or framing error) |
NOTES:
If bit 6 is set, the USART is busy (both data registers for sending are occupied) - if only bit 5 is
set, another byte can be sent to the USART.
Break INT: When the receiver line is held low (0) for more than the time it would take to receive
a full word (incl. start, data, parity and stop bits).
Framing error: Last bit is not a stop bit - occurs often when there is a speed mismatch.
Overrun error: Data in the buffer has not been read fast enough and is overwritten.
ADDRESS: BASE + 6 - READ ONLY - NAME: Modem Status Register (MSR)
| bit # | name |
| 0 | delta Clear To Send |
| 1 | delta Data Set Ready |
| 2 | Trailing Edge Ring Indicator |
| 3 | delta Data Carrier Detect |
| 4 | Clear To Send |
| 5 | Data Set Ready |
| 6 | Ring Indicator |
| 7 | Carrier Detect |
NOTES:
"delta" means that there was a change of the state in the line since the register was last read.
DIVISOR BYTE VALUES
| bps (bit/sec) | divisor | latch high byte | latch low byte |
| 50 | 2304 | 09h | 00h |
| 300 | 384 | 01h | 80h |
| 600 | 192 | 00h | C0h |
| 2400 | 48 | 00h | 30h |
| 4800 | 24 | 00h | 18h |
| 9600 | 12 | 00h | 0Ch |
| 19200 | 6 | 00h | 06h |
| 38400 | 3 | 00h | 03h |
| 57600 | 2 | 00h | 02h |
| 115200 | 1 | 00h | 01h |
Last-Modified: Sat, 04 Feb 2006 16:03:01 GMT
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