- Radio RF Electronics
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PIC - RAM Extension with 32k/64k SRAM
NOTE: These schematics have not been built and tested. They are just an idea for an RAM extension for the MicroChip PIC series
if an EEPROM is not useful due limited write cycles or the 256 byte of the PCF8570 I2C SRAM are too small.
Only 8 pins of a PIC are used to interface a SRAM (static ram) with up to 64kb storage space.
The idea is to read and write the data and RAM address via a serial signal, similar to the I2C or SPI bus.
Using HC574 would make the wiring simpler since data would couple straight across the latch rather than the convoluted in/out of '373.
Reading from the RAM:
- disable RAM
- set ADDRDATA to LOW (IC1 latch pins are output)
- shift low byte of the address into IC1 and store in latch IC3
- shift high byte of the address into IC1 and store in latch IC4
- set ADDRDATA to HIGH (latch pins are input)
- enable outputs of RAM
- load IC1 with SCLK
- disable RAM
- ADDRDATA = LOW: prepare for shifting out data
- shift data out of the shift register (IC1)
Writing to the RAM:
- disable RAM
- set ADDRDATA to LOW (latch pins are output)
- shift low byte of the address into IC1 and store in latch IC3
- shift high byte of the address into IC1 and store in latch IC4
- shift in data
- write to RAM
Here are a few notes for interfacing it:
RAM disabled:
/RAMOE = HIGH -> D0-D7 in high impedance state
/RAMWE = HIGH -> read, but outputs disabled
read RAM:
/RAMOE = LOW -> outputs enabled; data is on D0-D7
/RAMWE = HIGH -> read @ A0-A14 => D0-D7
write RAM:
/RAMOE = HIGH -> D0-7 in high impedance state
/RAMWE = LOW -> write D0-D7 @ A0-A14
ADDRESS LATCHES:
When LELB (latch enable high byte) or LEHB (LE low byte) goes from
HIGH to LOW, 1D-8D are stored.
ADDRDATA:
Select writing or reading:
ADDRDATA = LOW: Serial data @ SDATAIN is shifted into the IC with
CLK and displayed at QA-QH
ADDRDATA = HIGH: States @ QA-QH are loaded into IC1
Another approach, which uses only 6 PIC pins:
This one uses 3 shift-registers, which are cascaded. The (optional) data byte is shifted in, then the
high and low byte of the RAM address is shifted in.
Reading from the RAM:
- disable RAM
- ADDRDATA = LOW: shift in high address byte; shift in low address byte
- ADDRDATA = HIGH (IC1 latch pins are input)
- enable outputs of RAM
- load IC1 with SCLK
- disable RAM
- ADDRDATA = LOW: prepare for shifting out data
- shift data out of the shift register
Writing to the RAM:
- disable RAM
- ADDRDATA = LOW: shift in data byte; shift in high address byte; shift in low address byte
- write to RAM
Last-Modified: Thu, 10 Feb 2005 10:15:05 GMT
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